This application claims priority to Korean Patent Application No. 2004-85802, filed on Oct. 2, 2004 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to output driver circuits, and more particularly, to an output driver circuit with a pre-emphasis function that adjusts a control signal to an output driver.
2. Description of the Related Art
In general, a high-speed input/output (I/O) circuit inputs or outputs data at a speed of several Gbps and uses a pre-emphasis technique to reject Inter Symbol Interference (ISI) jitter. The pre-emphasis technique prevents reduction in timing margin of transmitted data, caused by a change in data transition time according to the pattern of data.
FIG. 1 is a block diagram of a conventional output driver circuit 10. The output driver circuit 10 includes an output control circuit 11, an output driver 12, and a pre-emphasis circuit 13. The output control circuit 11 generates a control signal CTL in response to an internal data signal DQI(N). The output driver 12 generates an output data signal DQO in response to the control signal CTL.
In a transmission system that transmits data at a speed of several Gbps, a resistance-capacitance (RC) time constant is determined by parasitic capacitance and parasitic resistances at a transmission channel. The RC time constant determines the time required for the output data signal DQO to reach a high voltage level VOH or a low voltage level VOL.
The swing range of the output data signal DQO decreases when a next internal data signal is input to the output driver circuit 10 before the level of the output data signal DQO reaches the high voltage level VOH or the low voltage level VOL. The swing range is decreased more significantly when the pattern of the internal data signal DQI(N) is continuously toggled.
Referring to FIG. 2, when the internal data signal DQI(N) consecutively has the same value, e.g., when the logic values thereof are 1111, the output data signal DQO swings fully to the high voltage level VOH. In contrast, when the logic value of the internal data signal DQI(N) is continuously changed, e.g., when the logic values are 1010, the output data signal DQO does not swing fully to the high voltage level VOH or the low voltage level VOL.
To prevent this problem, the pre-emphasis circuit 13 controls the level of the output data signal DQO such that the swing range of the output data signal DQO is overall equalized regardless of the pattern of the internal data signal DQI(N). The output driver 12 has a high-current driving capability to drive a transmission channel. The pre-emphasis circuit 13 must also have a high-current driving capability to control the level of the output data signal DQO. Accordingly, use of the conventional output driver circuit 10 consumes a large amount of current and increases the pre-emphasis ratio, thereby lowering the efficiency.